1. Field of the Invention
This invention relates to an image signal processing apparatus for performing image processing, such as filtering processing and the like, for image signals in a copier, a facsimile apparatus or the like.
2. Description of the Related Art
An ordinary digital image processing apparatus, such as a copier, a facsimile apparatus or the like, includes a plurality of units for performing matrix processing, such as digital filters or the like, used in edge emphasis and smoothing processing. Matrix processing for an image signal will now be described with reference to FIG. 10. A description will be provided of a case of using a 9.times.9 square matrix. The image signal is transferred according to a raster scanning method in units of a line.
In FIG. 10, reference numeral 601 represents an image signal for a line (line N+4) which is currently being transferred. Each of eight line buffers 602 delays an image signal for one line. Eight flip-flop circuits 603 are provided for each line. An image signal for the immediately preceding line N+3 is delayed by one line by the line buffer 602, and is input to the flip-flop circuits 603 for delay in the main scanning direction simultaneously with the image signal for line N+4. Similarly, each of image signals for lines N+2, N+1, N, N-1, N-2, N-3, and N-4 is delayed by one line by the corresponding line buffer 602, and is input to the flip-flop circuits 603 for delay in the main scanning direction in synchronization with the image signal for line N+4. Thus, image signals for nine consecutive lines in the sub-scanning direction constituting the 9.times.9 matrix are formed.
Each of the image signals for the nine lines is delayed by one pixel by each of the eight flip-flop circuits 603 to establish a delay in the main scanning direction provided for each line. Accordingly, by using one pixel signal not delayed by the flip-flop circuits 603 and eight pixel signals delayed thereby, nine consecutive pixel signals in the main scanning direction constituting the 9.times.9 matrix are formed. The 9.times.9 pixel signals are input to a calculation circuit 604, which performs predetermined calculations and outputs an image signal 605 for line N.
A description has been provided of a matrix image processing unit in an ordinary digital image processing apparatus. In recent digital image processing apparatuses, however, high-speed transfer of an image signal is indispensable due to the synergistic effect of demand for improved processing capability and demand for high resolution. The speed of the circuitry of the matrix image processing unit having the above-described configuration is insufficient for realizing such high-speed transfer. Hence, it is necessary to realize high-speed transfer of an image signal using a low-speed matrix image processing unit.
For that purpose, a method of reducing the transfer speed by rearranging the image signal serially transferred at a high speed in the order of pixels into a parallel state can be considered. For example, in pixel parallel processing in which parallel processing is performed in units of a pixel, the transfer speed can be reduced to 1/2 if parallel processing is performed for two pixels, and the transfer speed can be reduced to 1/3 if parallel processing is performed for three pixels. Alternatively, for example, line division parallel processing in which parallel processing is performed by dividing an image signal for one line into a plurality of signals in the direction of the line can also be considered.
In such parallel processing, as a result of performing relatively-low-speed image processing in parallel, high-speed image processing is realized, so that an image signal can be transferred at a high speed.
However, the circuit configuration when performing the above-described image processing using a matrix by parallel processing becomes very complicated. FIG. 11 illustrates the circuit configuration in such a case. In FIG. 11, a case of performing parallel processing for four pixels in order to reduce the transfer speed to 1/4 is illustrated.
As in the case of FIG. 10, reference numeral 701 represents an input image signal for line N+4. Four pixel signals n, n+1, n+2 and n+3 for line N+4, which are consecutive in the main scanning direction as a result of serial/parallel conversion in preprocessing, are simultaneously input in parallel. In order to perform the same 9.times.9 matrix processing as in the above-described case for the four pixel signals input in parallel, 32 line buffers 702 for forming image signals for 9 lines in the sub scanning direction are required. Accordingly, the number of line buffers is four times the number in the case of FIG. 10.
Since one line is divided into four portions, the capacity required for each line buffer 702 is 1/4 of the capacity in the case of FIG. 10. Accordingly, the total capacity of the buffers is the same as that in the case of FIG. 10. Actually, however, since the available lineup of ordinary line buffers lacks such variations in capacity, the total cost of line buffers is considerably increased.
In general, other portions than the line buffers 702, i.e., the portions of flip-flop circuits 703 and a calculation circuit 704, in the matrix image processing unit 105 are provided in the form of a one-chip ASIC (application specific integrated circuit). When providing a one-chip ASIC for this pixel parallel processing, the number of terminals for input signals causes a big problem. That is, if an image signal for each input is assumed to comprise 8 bits, the total required number of terminals of the ASIC becomes: EQU 9 (lines).times.4 (pixels in parallel).times.8 (bits)=288,
and therefore it is very difficult to produce such an ASIC. Accordingly, the pixel parallel processing has two problems, i.e., an increase in the cost of the line buffers, and a limitation in providing an ASIC.